Leading One Detectors: Evolutionary Approach PDF

Keywords

Leading one detector, Genetic, Algorithm, Evolvable Hardware, Floating point multiplier.

Abstract

Leading One Detector (LOD) is an important and preliminary stage used for the normalization process in floating point multiplication, floating point addition/subtraction and in logarithmic converters. In this paper the authors propose various gate level architectures for the LOD. The LOD circuit is evolved using the evolutionary algorithm (EA) and using the evolved lower order LOD gate structure, various higher order LOD circuits are constructed using a hierarchical methodology. To obtain better results, the evolutionary algorithm is modified and a novel shuffling operation is performed to prevent the algorithm from settling in the local minima. The convergence and the robustness of the evolutionary algorithm is verified using standard test functions. The constructed LOD circuits are synthesized using Cadence® RTL Compiler® using TSMC 180nm library. The results obtained in terms of cell area and power of the elite LOD circuits show that the proposed evolved-architecture outperforms the existing circuits. The proposed architectures show a maximum of 31.18% improvements in Cell area and 31.27% in power for the 64-bitLOD circuit with an increase of 3.9% in the propagation delay.